From 799fed0a7cc508bd42d0eb6aa576cb569ff60288 Mon Sep 17 00:00:00 2001 From: "kaf24@scramble.cl.cam.ac.uk" Date: Tue, 21 Dec 2004 17:38:54 +0000 Subject: [PATCH] bitkeeper revision 1.1159.1.496 (41c85faeMBUejFtICiJueb_Xdh8yJA) Priv-op emulation in Xen, for RDMSR/WRMSR/WBINVD. Cleaned up Linux a bit as a result. --- .rootkeys | 4 - linux-2.4.28-xen-sparse/include/asm-xen/msr.h | 138 --------- .../include/asm-xen/asm-i386/msr.h | 273 ------------------ patches/linux-2.6.9/drm.patch | 12 - patches/linux-2.6.9/nettel.patch | 30 -- xen/arch/x86/traps.c | 50 ++++ xen/arch/x86/x86_32/mm.c | 10 - xen/arch/x86/x86_64/mm.c | 18 +- xen/common/schedule.c | 22 +- xen/common/trace.c | 7 +- xen/include/asm-x86/mm.h | 2 - xen/include/asm-x86/shadow.h | 3 - 12 files changed, 73 insertions(+), 496 deletions(-) delete mode 100644 linux-2.4.28-xen-sparse/include/asm-xen/msr.h delete mode 100644 linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/msr.h delete mode 100644 patches/linux-2.6.9/drm.patch delete mode 100644 patches/linux-2.6.9/nettel.patch diff --git a/.rootkeys b/.rootkeys index c6ce0aa40a..91d41fdfc8 100644 --- a/.rootkeys +++ b/.rootkeys @@ -98,7 +98,6 @@ 40d70c240tW7TWArl1VUgIFH2nVO1A linux-2.4.28-xen-sparse/include/asm-xen/keyboard.h 3e5a4e678ddsQOpbSiRdy1GRcDc9WA linux-2.4.28-xen-sparse/include/asm-xen/mmu_context.h 40d06e5b2YWInUX1Xv9amVANwd_2Xg linux-2.4.28-xen-sparse/include/asm-xen/module.h -3f8707e7ZmZ6TxyX0ZUEfvhA2Pb_xQ linux-2.4.28-xen-sparse/include/asm-xen/msr.h 3e5a4e67mnQfh-R8KcQCaVo2Oho6yg linux-2.4.28-xen-sparse/include/asm-xen/page.h 409ba2e7ZfV5hqTvIzxLtpClnxtIzg linux-2.4.28-xen-sparse/include/asm-xen/pci.h 3e5a4e67uTYU5oEnIDjxuaez8njjqg linux-2.4.28-xen-sparse/include/asm-xen/pgalloc.h @@ -232,7 +231,6 @@ 40f5623arsFXkGdPvIqvFi3yFXGR0Q linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/mach-xen/setup_arch_pre.h 41811f07Iri9hrvs97t-baxmhOwWDQ linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/mach-xen/smpboot_hooks.h 4120f807GCO0uqsLqdZj9csxR1Wthw linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/mmu_context.h -40f5623aFTyFTR-vdiA-KaGxk5JOKQ linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/msr.h 40f5623adgjZq9nAgCt0IXdWl7udSA linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/page.h 40f5623a54NuG-7qHihGYmw4wWQnMA linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/param.h 41137cc1kkvg0cg7uxddcEfjL7L67w linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/pci.h @@ -306,8 +304,6 @@ 413cb3b5F56TvQWAmO5TsuzhtzLFPQ netbsd-2.0-xen-sparse/sys/arch/xen/xen/xenkbc.c 413cb3b53nyOv1OIeDSsCXhBFDXvJA netbsd-2.0-xen-sparse/sys/nfs/files.nfs 413aa1d0oNP8HXLvfPuMe6cSroUfSA patches/linux-2.6.9/agpgart.patch -413aa1d0ewvSv-ohnNnQQNGsbPTTNA patches/linux-2.6.9/drm.patch -418abc69J3F638vPO9MYoDGeYilxoQ patches/linux-2.6.9/nettel.patch 40e1b09db5mN69Ijj0X_Eol-S7dXiw tools/Make.defs 3f776bd1Hy9rn69ntXBhPReUFw9IEA tools/Makefile 4124b307nRyK3dhn1hAsvrY76NuV3g tools/check/Makefile diff --git a/linux-2.4.28-xen-sparse/include/asm-xen/msr.h b/linux-2.4.28-xen-sparse/include/asm-xen/msr.h deleted file mode 100644 index 1a2c8765a8..0000000000 --- a/linux-2.4.28-xen-sparse/include/asm-xen/msr.h +++ /dev/null @@ -1,138 +0,0 @@ -#ifndef __ASM_MSR_H -#define __ASM_MSR_H - -/* - * Access to machine-specific registers (available on 586 and better only) - * Note: the rd* operations modify the parameters directly (without using - * pointer indirection), this allows gcc to optimize better - */ - -#define rdmsr(msr,val1,val2) \ -{ \ - dom0_op_t op; \ - op.cmd = DOM0_MSR; \ - op.u.msr.write = 0; \ - op.u.msr.msr = msr; \ - op.u.msr.cpu_mask = (1 << current->processor); \ - HYPERVISOR_dom0_op(&op); \ - val1 = op.u.msr.out1; \ - val2 = op.u.msr.out2; \ -} - -#define wrmsr(msr,val1,val2) \ -{ \ - dom0_op_t op; \ - op.cmd = DOM0_MSR; \ - op.u.msr.write = 1; \ - op.u.msr.cpu_mask = (1 << current->processor); \ - op.u.msr.msr = msr; \ - op.u.msr.in1 = val1; \ - op.u.msr.in2 = val2; \ - HYPERVISOR_dom0_op(&op); \ -} - -#define rdtsc(low,high) \ - __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) - -#define rdtscl(low) \ - __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx") - -#define rdtscll(val) \ - __asm__ __volatile__("rdtsc" : "=A" (val)) - -#define write_tsc(val1,val2) wrmsr(0x10, val1, val2) - -#define rdpmc(counter,low,high) \ - __asm__ __volatile__("rdpmc" \ - : "=a" (low), "=d" (high) \ - : "c" (counter)) - -/* symbolic names for some interesting MSRs */ -/* Intel defined MSRs. */ -#define MSR_IA32_P5_MC_ADDR 0 -#define MSR_IA32_P5_MC_TYPE 1 -#define MSR_IA32_PLATFORM_ID 0x17 -#define MSR_IA32_EBL_CR_POWERON 0x2a - -#define MSR_IA32_APICBASE 0x1b -#define MSR_IA32_APICBASE_BSP (1<<8) -#define MSR_IA32_APICBASE_ENABLE (1<<11) -#define MSR_IA32_APICBASE_BASE (0xfffff<<12) - -#define MSR_IA32_UCODE_WRITE 0x79 -#define MSR_IA32_UCODE_REV 0x8b - -#define MSR_IA32_BBL_CR_CTL 0x119 - -#define MSR_IA32_MCG_CAP 0x179 -#define MSR_IA32_MCG_STATUS 0x17a -#define MSR_IA32_MCG_CTL 0x17b - -#define MSR_IA32_THERM_CONTROL 0x19a -#define MSR_IA32_THERM_INTERRUPT 0x19b -#define MSR_IA32_THERM_STATUS 0x19c -#define MSR_IA32_MISC_ENABLE 0x1a0 - -#define MSR_IA32_DEBUGCTLMSR 0x1d9 -#define MSR_IA32_LASTBRANCHFROMIP 0x1db -#define MSR_IA32_LASTBRANCHTOIP 0x1dc -#define MSR_IA32_LASTINTFROMIP 0x1dd -#define MSR_IA32_LASTINTTOIP 0x1de - -#define MSR_IA32_MC0_CTL 0x400 -#define MSR_IA32_MC0_STATUS 0x401 -#define MSR_IA32_MC0_ADDR 0x402 -#define MSR_IA32_MC0_MISC 0x403 - -#define MSR_P6_PERFCTR0 0xc1 -#define MSR_P6_PERFCTR1 0xc2 -#define MSR_P6_EVNTSEL0 0x186 -#define MSR_P6_EVNTSEL1 0x187 - -#define MSR_IA32_PERF_STATUS 0x198 -#define MSR_IA32_PERF_CTL 0x199 - -/* AMD Defined MSRs */ -#define MSR_K6_EFER 0xC0000080 -#define MSR_K6_STAR 0xC0000081 -#define MSR_K6_WHCR 0xC0000082 -#define MSR_K6_UWCCR 0xC0000085 -#define MSR_K6_EPMR 0xC0000086 -#define MSR_K6_PSOR 0xC0000087 -#define MSR_K6_PFIR 0xC0000088 - -#define MSR_K7_EVNTSEL0 0xC0010000 -#define MSR_K7_PERFCTR0 0xC0010004 -#define MSR_K7_HWCR 0xC0010015 -#define MSR_K7_CLK_CTL 0xC001001b -#define MSR_K7_FID_VID_CTL 0xC0010041 -#define MSR_K7_VID_STATUS 0xC0010042 - -/* Centaur-Hauls/IDT defined MSRs. */ -#define MSR_IDT_FCR1 0x107 -#define MSR_IDT_FCR2 0x108 -#define MSR_IDT_FCR3 0x109 -#define MSR_IDT_FCR4 0x10a - -#define MSR_IDT_MCR0 0x110 -#define MSR_IDT_MCR1 0x111 -#define MSR_IDT_MCR2 0x112 -#define MSR_IDT_MCR3 0x113 -#define MSR_IDT_MCR4 0x114 -#define MSR_IDT_MCR5 0x115 -#define MSR_IDT_MCR6 0x116 -#define MSR_IDT_MCR7 0x117 -#define MSR_IDT_MCR_CTRL 0x120 - -/* VIA Cyrix defined MSRs*/ -#define MSR_VIA_FCR 0x1107 -#define MSR_VIA_LONGHAUL 0x110a -#define MSR_VIA_BCR2 0x1147 - -/* Transmeta defined MSRs */ -#define MSR_TMTA_LONGRUN_CTRL 0x80868010 -#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 -#define MSR_TMTA_LRTI_READOUT 0x80868018 -#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a - -#endif /* __ASM_MSR_H */ diff --git a/linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/msr.h b/linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/msr.h deleted file mode 100644 index 8bd09e21f0..0000000000 --- a/linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/msr.h +++ /dev/null @@ -1,273 +0,0 @@ -#ifndef __ASM_MSR_H -#define __ASM_MSR_H - -#include - -/* - * Access to machine-specific registers (available on 586 and better only) - * Note: the rd* operations modify the parameters directly (without using - * pointer indirection), this allows gcc to optimize better - */ - -extern int get_smp_processor_id(void); - -#define rdmsr(_msr,_val1,_val2) do { \ - dom0_op_t op; \ - op.cmd = DOM0_MSR; \ - op.u.msr.write = 0; \ - op.u.msr.msr = (_msr); \ - op.u.msr.cpu_mask = (1 << get_smp_processor_id()); \ - HYPERVISOR_dom0_op(&op); \ - (_val1) = op.u.msr.out1; \ - (_val2) = op.u.msr.out2; \ -} while(0) - -#define wrmsr(_msr,_val1,_val2) do { \ - dom0_op_t op; \ - op.cmd = DOM0_MSR; \ - op.u.msr.write = 1; \ - op.u.msr.cpu_mask = (1 << get_smp_processor_id()); \ - op.u.msr.msr = (_msr); \ - op.u.msr.in1 = (_val1); \ - op.u.msr.in2 = (_val2); \ - HYPERVISOR_dom0_op(&op); \ -} while(0) - -#define rdmsrl(msr,val) do { \ - unsigned long l__,h__; \ - rdmsr (msr, l__, h__); \ - val = l__; \ - val |= ((u64)h__<<32); \ -} while(0) - -static inline void wrmsrl (unsigned long msr, unsigned long long val) -{ - unsigned long lo, hi; - lo = (unsigned long) val; - hi = val >> 32; - wrmsr (msr, lo, hi); -} - -#define rdtsc(low,high) \ - __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) - -#define rdtscl(low) \ - __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx") - -#define rdtscll(val) \ - __asm__ __volatile__("rdtsc" : "=A" (val)) - -#define write_tsc(val1,val2) wrmsr(0x10, val1, val2) - -#define rdpmc(counter,low,high) \ - __asm__ __volatile__("rdpmc" \ - : "=a" (low), "=d" (high) \ - : "c" (counter)) - -/* symbolic names for some interesting MSRs */ -/* Intel defined MSRs. */ -#define MSR_IA32_P5_MC_ADDR 0 -#define MSR_IA32_P5_MC_TYPE 1 -#define MSR_IA32_PLATFORM_ID 0x17 -#define MSR_IA32_EBL_CR_POWERON 0x2a - -#define MSR_IA32_APICBASE 0x1b -#define MSR_IA32_APICBASE_BSP (1<<8) -#define MSR_IA32_APICBASE_ENABLE (1<<11) -#define MSR_IA32_APICBASE_BASE (0xfffff<<12) - -#define MSR_IA32_UCODE_WRITE 0x79 -#define MSR_IA32_UCODE_REV 0x8b - -#define MSR_P6_PERFCTR0 0xc1 -#define MSR_P6_PERFCTR1 0xc2 - -#define MSR_IA32_BBL_CR_CTL 0x119 - -#define MSR_IA32_SYSENTER_CS 0x174 -#define MSR_IA32_SYSENTER_ESP 0x175 -#define MSR_IA32_SYSENTER_EIP 0x176 - -#define MSR_IA32_MCG_CAP 0x179 -#define MSR_IA32_MCG_STATUS 0x17a -#define MSR_IA32_MCG_CTL 0x17b - -/* P4/Xeon+ specific */ -#define MSR_IA32_MCG_EAX 0x180 -#define MSR_IA32_MCG_EBX 0x181 -#define MSR_IA32_MCG_ECX 0x182 -#define MSR_IA32_MCG_EDX 0x183 -#define MSR_IA32_MCG_ESI 0x184 -#define MSR_IA32_MCG_EDI 0x185 -#define MSR_IA32_MCG_EBP 0x186 -#define MSR_IA32_MCG_ESP 0x187 -#define MSR_IA32_MCG_EFLAGS 0x188 -#define MSR_IA32_MCG_EIP 0x189 -#define MSR_IA32_MCG_RESERVED 0x18A - -#define MSR_P6_EVNTSEL0 0x186 -#define MSR_P6_EVNTSEL1 0x187 - -#define MSR_IA32_PERF_STATUS 0x198 -#define MSR_IA32_PERF_CTL 0x199 - -#define MSR_IA32_THERM_CONTROL 0x19a -#define MSR_IA32_THERM_INTERRUPT 0x19b -#define MSR_IA32_THERM_STATUS 0x19c -#define MSR_IA32_MISC_ENABLE 0x1a0 - -#define MSR_IA32_DEBUGCTLMSR 0x1d9 -#define MSR_IA32_LASTBRANCHFROMIP 0x1db -#define MSR_IA32_LASTBRANCHTOIP 0x1dc -#define MSR_IA32_LASTINTFROMIP 0x1dd -#define MSR_IA32_LASTINTTOIP 0x1de - -#define MSR_IA32_MC0_CTL 0x400 -#define MSR_IA32_MC0_STATUS 0x401 -#define MSR_IA32_MC0_ADDR 0x402 -#define MSR_IA32_MC0_MISC 0x403 - -/* Pentium IV performance counter MSRs */ -#define MSR_P4_BPU_PERFCTR0 0x300 -#define MSR_P4_BPU_PERFCTR1 0x301 -#define MSR_P4_BPU_PERFCTR2 0x302 -#define MSR_P4_BPU_PERFCTR3 0x303 -#define MSR_P4_MS_PERFCTR0 0x304 -#define MSR_P4_MS_PERFCTR1 0x305 -#define MSR_P4_MS_PERFCTR2 0x306 -#define MSR_P4_MS_PERFCTR3 0x307 -#define MSR_P4_FLAME_PERFCTR0 0x308 -#define MSR_P4_FLAME_PERFCTR1 0x309 -#define MSR_P4_FLAME_PERFCTR2 0x30a -#define MSR_P4_FLAME_PERFCTR3 0x30b -#define MSR_P4_IQ_PERFCTR0 0x30c -#define MSR_P4_IQ_PERFCTR1 0x30d -#define MSR_P4_IQ_PERFCTR2 0x30e -#define MSR_P4_IQ_PERFCTR3 0x30f -#define MSR_P4_IQ_PERFCTR4 0x310 -#define MSR_P4_IQ_PERFCTR5 0x311 -#define MSR_P4_BPU_CCCR0 0x360 -#define MSR_P4_BPU_CCCR1 0x361 -#define MSR_P4_BPU_CCCR2 0x362 -#define MSR_P4_BPU_CCCR3 0x363 -#define MSR_P4_MS_CCCR0 0x364 -#define MSR_P4_MS_CCCR1 0x365 -#define MSR_P4_MS_CCCR2 0x366 -#define MSR_P4_MS_CCCR3 0x367 -#define MSR_P4_FLAME_CCCR0 0x368 -#define MSR_P4_FLAME_CCCR1 0x369 -#define MSR_P4_FLAME_CCCR2 0x36a -#define MSR_P4_FLAME_CCCR3 0x36b -#define MSR_P4_IQ_CCCR0 0x36c -#define MSR_P4_IQ_CCCR1 0x36d -#define MSR_P4_IQ_CCCR2 0x36e -#define MSR_P4_IQ_CCCR3 0x36f -#define MSR_P4_IQ_CCCR4 0x370 -#define MSR_P4_IQ_CCCR5 0x371 -#define MSR_P4_ALF_ESCR0 0x3ca -#define MSR_P4_ALF_ESCR1 0x3cb -#define MSR_P4_BPU_ESCR0 0x3b2 -#define MSR_P4_BPU_ESCR1 0x3b3 -#define MSR_P4_BSU_ESCR0 0x3a0 -#define MSR_P4_BSU_ESCR1 0x3a1 -#define MSR_P4_CRU_ESCR0 0x3b8 -#define MSR_P4_CRU_ESCR1 0x3b9 -#define MSR_P4_CRU_ESCR2 0x3cc -#define MSR_P4_CRU_ESCR3 0x3cd -#define MSR_P4_CRU_ESCR4 0x3e0 -#define MSR_P4_CRU_ESCR5 0x3e1 -#define MSR_P4_DAC_ESCR0 0x3a8 -#define MSR_P4_DAC_ESCR1 0x3a9 -#define MSR_P4_FIRM_ESCR0 0x3a4 -#define MSR_P4_FIRM_ESCR1 0x3a5 -#define MSR_P4_FLAME_ESCR0 0x3a6 -#define MSR_P4_FLAME_ESCR1 0x3a7 -#define MSR_P4_FSB_ESCR0 0x3a2 -#define MSR_P4_FSB_ESCR1 0x3a3 -#define MSR_P4_IQ_ESCR0 0x3ba -#define MSR_P4_IQ_ESCR1 0x3bb -#define MSR_P4_IS_ESCR0 0x3b4 -#define MSR_P4_IS_ESCR1 0x3b5 -#define MSR_P4_ITLB_ESCR0 0x3b6 -#define MSR_P4_ITLB_ESCR1 0x3b7 -#define MSR_P4_IX_ESCR0 0x3c8 -#define MSR_P4_IX_ESCR1 0x3c9 -#define MSR_P4_MOB_ESCR0 0x3aa -#define MSR_P4_MOB_ESCR1 0x3ab -#define MSR_P4_MS_ESCR0 0x3c0 -#define MSR_P4_MS_ESCR1 0x3c1 -#define MSR_P4_PMH_ESCR0 0x3ac -#define MSR_P4_PMH_ESCR1 0x3ad -#define MSR_P4_RAT_ESCR0 0x3bc -#define MSR_P4_RAT_ESCR1 0x3bd -#define MSR_P4_SAAT_ESCR0 0x3ae -#define MSR_P4_SAAT_ESCR1 0x3af -#define MSR_P4_SSU_ESCR0 0x3be -#define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */ -#define MSR_P4_TBPU_ESCR0 0x3c2 -#define MSR_P4_TBPU_ESCR1 0x3c3 -#define MSR_P4_TC_ESCR0 0x3c4 -#define MSR_P4_TC_ESCR1 0x3c5 -#define MSR_P4_U2L_ESCR0 0x3b0 -#define MSR_P4_U2L_ESCR1 0x3b1 - -/* AMD Defined MSRs */ -#define MSR_K6_EFER 0xC0000080 -#define MSR_K6_STAR 0xC0000081 -#define MSR_K6_WHCR 0xC0000082 -#define MSR_K6_UWCCR 0xC0000085 -#define MSR_K6_EPMR 0xC0000086 -#define MSR_K6_PSOR 0xC0000087 -#define MSR_K6_PFIR 0xC0000088 - -#define MSR_K7_EVNTSEL0 0xC0010000 -#define MSR_K7_EVNTSEL1 0xC0010001 -#define MSR_K7_EVNTSEL2 0xC0010002 -#define MSR_K7_EVNTSEL3 0xC0010003 -#define MSR_K7_PERFCTR0 0xC0010004 -#define MSR_K7_PERFCTR1 0xC0010005 -#define MSR_K7_PERFCTR2 0xC0010006 -#define MSR_K7_PERFCTR3 0xC0010007 -#define MSR_K7_HWCR 0xC0010015 -#define MSR_K7_CLK_CTL 0xC001001b -#define MSR_K7_FID_VID_CTL 0xC0010041 -#define MSR_K7_FID_VID_STATUS 0xC0010042 - -/* extended feature register */ -#define MSR_EFER 0xc0000080 - -/* EFER bits: */ - -/* Execute Disable enable */ -#define _EFER_NX 11 -#define EFER_NX (1<<_EFER_NX) - -/* Centaur-Hauls/IDT defined MSRs. */ -#define MSR_IDT_FCR1 0x107 -#define MSR_IDT_FCR2 0x108 -#define MSR_IDT_FCR3 0x109 -#define MSR_IDT_FCR4 0x10a - -#define MSR_IDT_MCR0 0x110 -#define MSR_IDT_MCR1 0x111 -#define MSR_IDT_MCR2 0x112 -#define MSR_IDT_MCR3 0x113 -#define MSR_IDT_MCR4 0x114 -#define MSR_IDT_MCR5 0x115 -#define MSR_IDT_MCR6 0x116 -#define MSR_IDT_MCR7 0x117 -#define MSR_IDT_MCR_CTRL 0x120 - -/* VIA Cyrix defined MSRs*/ -#define MSR_VIA_FCR 0x1107 -#define MSR_VIA_LONGHAUL 0x110a -#define MSR_VIA_RNG 0x110b -#define MSR_VIA_BCR2 0x1147 - -/* Transmeta defined MSRs */ -#define MSR_TMTA_LONGRUN_CTRL 0x80868010 -#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 -#define MSR_TMTA_LRTI_READOUT 0x80868018 -#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a - -#endif /* __ASM_MSR_H */ diff --git a/patches/linux-2.6.9/drm.patch b/patches/linux-2.6.9/drm.patch deleted file mode 100644 index f39d5cb3d0..0000000000 --- a/patches/linux-2.6.9/drm.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -ur linux-2.6.9/drivers/char/drm/ati_pcigart.h linux-2.6.9-new/drivers/char/drm/ati_pcigart.h ---- linux-2.6.9/drivers/char/drm/ati_pcigart.h 2004-10-18 22:55:07.000000000 +0100 -+++ linux-2.6.9-new/drivers/char/drm/ati_pcigart.h 2004-11-28 19:42:41.000000000 +0000 -@@ -158,7 +158,7 @@ - ret = 1; - - #if defined(__i386__) || defined(__x86_64__) -- asm volatile ( "wbinvd" ::: "memory" ); -+ wbinvd(); - #else - mb(); - #endif diff --git a/patches/linux-2.6.9/nettel.patch b/patches/linux-2.6.9/nettel.patch deleted file mode 100644 index e8dd94a33a..0000000000 --- a/patches/linux-2.6.9/nettel.patch +++ /dev/null @@ -1,30 +0,0 @@ -diff -ur linux-2.6.9/drivers/mtd/maps/nettel.c linux-2.6.9-new/drivers/mtd/maps/nettel.c ---- linux-2.6.9/drivers/mtd/maps/nettel.c 2004-10-18 22:53:44.000000000 +0100 -+++ linux-2.6.9-new/drivers/mtd/maps/nettel.c 2004-11-28 19:45:35.000000000 +0000 -@@ -270,7 +270,7 @@ - maxsize = AMD_WINDOW_MAXSIZE; - - *amdpar = SC520_PAR(SC520_PAR_BOOTCS, amdaddr, maxsize); -- __asm__ ("wbinvd"); -+ wbinvd(); - - nettel_amd_map.phys = amdaddr; - nettel_amd_map.virt = (unsigned long) -@@ -382,7 +382,7 @@ - */ - intel1addr = intel0addr + intel0size; - *intel1par = SC520_PAR(intel1cs, intel1addr, maxsize); -- __asm__ ("wbinvd"); -+ wbinvd(); - - maxsize += intel0size; - -@@ -408,7 +408,7 @@ - intel1size = intel_mtd->size - intel0size; - if (intel1size > 0) { - *intel1par = SC520_PAR(intel1cs, intel1addr, intel1size); -- __asm__ ("wbinvd"); -+ wbinvd(); - } else { - *intel1par = 0; - } diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 59ff112bd1..d044230bd7 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -51,6 +51,7 @@ #include #include #include +#include #if defined(__i386__) @@ -481,6 +482,49 @@ asmlinkage int do_page_fault(struct xen_regs *regs) return 0; } +static int emulate_privileged_op(struct xen_regs *regs) +{ + u16 opcode; + + if ( get_user(opcode, (u16 *)regs->eip) || ((opcode & 0xff) != 0x0f) ) + return 0; + + switch ( opcode >> 8 ) + { + case 0x09: /* WBINVD */ + if ( !IS_CAPABLE_PHYSDEV(current->domain) ) + { + DPRINTK("Non-physdev domain attempted WBINVD.\n"); + return 0; + } + wbinvd(); + regs->eip += 2; + return 1; + + case 0x30: /* WRMSR */ + if ( !IS_PRIV(current->domain) ) + { + DPRINTK("Non-priv domain attempted WRMSR.\n"); + return 0; + } + wrmsr(regs->ecx, regs->eax, regs->edx); + regs->eip += 2; + return 1; + + case 0x32: /* RDMSR */ + if ( !IS_PRIV(current->domain) ) + { + DPRINTK("Non-priv domain attempted RDMSR.\n"); + return 0; + } + rdmsr(regs->ecx, regs->eax, regs->edx); + regs->eip += 2; + return 1; + } + + return 0; +} + asmlinkage int do_general_protection(struct xen_regs *regs) { struct exec_domain *ed = current; @@ -529,6 +573,12 @@ asmlinkage int do_general_protection(struct xen_regs *regs) } } + /* Emulate some simple privileged instructions when exec'ed in ring 1. */ + if ( (regs->error_code == 0) && + RING_1(regs) && + emulate_privileged_op(regs) ) + return 0; + #if defined(__i386__) if ( VM_ASSIST(d, VMASST_TYPE_4gb_segments) && (regs->error_code == 0) && diff --git a/xen/arch/x86/x86_32/mm.c b/xen/arch/x86/x86_32/mm.c index 401ae63a81..ab35a5a99f 100644 --- a/xen/arch/x86/x86_32/mm.c +++ b/xen/arch/x86/x86_32/mm.c @@ -466,14 +466,4 @@ void memguard_unguard_range(void *p, unsigned long l) __memguard_change_range(p, l, 0); } -int memguard_is_guarded(void *p) -{ - l1_pgentry_t *l1; - l2_pgentry_t *l2; - unsigned long _p = (unsigned long)p; - l2 = &idle_pg_table[l2_table_offset(_p)]; - l1 = l2_pgentry_to_l1(*l2) + l1_table_offset(_p); - return !(l1_pgentry_val(*l1) & _PAGE_PRESENT); -} - #endif diff --git a/xen/arch/x86/x86_64/mm.c b/xen/arch/x86/x86_64/mm.c index 90fd586d00..fe11c2cf3d 100644 --- a/xen/arch/x86/x86_64/mm.c +++ b/xen/arch/x86/x86_64/mm.c @@ -363,6 +363,14 @@ long do_update_descriptor( #ifdef MEMORY_GUARD +#if 1 + +void *memguard_init(void *heap_start) { return heap_start; } +void memguard_guard_range(void *p, unsigned long l) {} +void memguard_unguard_range(void *p, unsigned long l) {} + +#else + void *memguard_init(void *heap_start) { l1_pgentry_t *l1; @@ -425,14 +433,6 @@ void memguard_unguard_range(void *p, unsigned long l) __memguard_change_range(p, l, 0); } -int memguard_is_guarded(void *p) -{ - l1_pgentry_t *l1; - l2_pgentry_t *l2; - unsigned long _p = (unsigned long)p; - l2 = &idle_pg_table[l2_table_offset(_p)]; - l1 = l2_pgentry_to_l1(*l2) + l1_table_offset(_p); - return !(l1_pgentry_val(*l1) & _PAGE_PRESENT); -} +#endif #endif diff --git a/xen/common/schedule.c b/xen/common/schedule.c index acc21e2a35..94af2ee176 100644 --- a/xen/common/schedule.c +++ b/xen/common/schedule.c @@ -224,24 +224,24 @@ void domain_sleep(struct exec_domain *d) } } -void domain_wake(struct exec_domain *d) +void domain_wake(struct exec_domain *ed) { unsigned long flags; - spin_lock_irqsave(&schedule_data[d->processor].schedule_lock, flags); + spin_lock_irqsave(&schedule_data[ed->processor].schedule_lock, flags); - if ( likely(domain_runnable(d)) ) + if ( likely(domain_runnable(ed)) ) { - TRACE_2D(TRC_SCHED_WAKE, d->id, d); - SCHED_OP(wake, d); + TRACE_2D(TRC_SCHED_WAKE, ed->domain->id, ed); + SCHED_OP(wake, ed); #ifdef WAKE_HISTO - d->wokenup = NOW(); + ed->wokenup = NOW(); #endif } - clear_bit(EDF_MIGRATED, &d->ed_flags); + clear_bit(EDF_MIGRATED, &ed->ed_flags); - spin_unlock_irqrestore(&schedule_data[d->processor].schedule_lock, flags); + spin_unlock_irqrestore(&schedule_data[ed->processor].schedule_lock, flags); } /* Block the currently-executing domain until a pertinent event occurs. */ @@ -250,7 +250,7 @@ long do_block(void) ASSERT(current->domain->id != IDLE_DOMAIN_ID); current->vcpu_info->evtchn_upcall_mask = 0; set_bit(EDF_BLOCKED, ¤t->ed_flags); - TRACE_2D(TRC_SCHED_BLOCK, current->id, current); + TRACE_2D(TRC_SCHED_BLOCK, current->domain->id, current); __enter_scheduler(); return 0; } @@ -258,7 +258,7 @@ long do_block(void) /* Voluntarily yield the processor for this allocation. */ static long do_yield(void) { - TRACE_2D(TRC_SCHED_YIELD, current->id, current); + TRACE_2D(TRC_SCHED_YIELD, current->domain->id, current); __enter_scheduler(); return 0; } @@ -447,7 +447,7 @@ void __enter_scheduler(void) } #endif - TRACE_2D(TRC_SCHED_SWITCH, next->id, next); + TRACE_2D(TRC_SCHED_SWITCH, next->domain->id, next); switch_to(prev, next); diff --git a/xen/common/trace.c b/xen/common/trace.c index d4954256ce..4826978b59 100644 --- a/xen/common/trace.c +++ b/xen/common/trace.c @@ -28,6 +28,8 @@ #include #include +extern unsigned int opt_tbuf_size; + /* Pointers to the meta-data objects for all system trace buffers */ struct t_buf *t_bufs[NR_CPUS]; @@ -43,7 +45,6 @@ int tb_init_done = 0; */ void init_trace_bufs(void) { - extern int opt_tbuf_size; int i, order; unsigned long nr_pages; char *rawbuf; @@ -102,10 +103,8 @@ void init_trace_bufs(void) */ int get_tb_info(dom0_gettbufs_t *st) { - if(tb_init_done) + if ( tb_init_done ) { - extern unsigned int opt_tbuf_size; - st->mach_addr = __pa(t_bufs[0]); st->size = opt_tbuf_size * PAGE_SIZE; diff --git a/xen/include/asm-x86/mm.h b/xen/include/asm-x86/mm.h index 652084f117..c5403fe813 100644 --- a/xen/include/asm-x86/mm.h +++ b/xen/include/asm-x86/mm.h @@ -237,12 +237,10 @@ extern unsigned long *phys_to_machine_mapping; void *memguard_init(void *heap_start); void memguard_guard_range(void *p, unsigned long l); void memguard_unguard_range(void *p, unsigned long l); -int memguard_is_guarded(void *p); #else #define memguard_init(_s) (_s) #define memguard_guard_range(_p,_l) ((void)0) #define memguard_unguard_range(_p,_l) ((void)0) -#define memguard_is_guarded(_p) (0) #endif diff --git a/xen/include/asm-x86/shadow.h b/xen/include/asm-x86/shadow.h index 29c9dbb5ca..b22215688e 100644 --- a/xen/include/asm-x86/shadow.h +++ b/xen/include/asm-x86/shadow.h @@ -186,15 +186,12 @@ static inline int __mark_dirty( struct mm_struct *m, unsigned int mfn) #ifndef NDEBUG else if ( mfn < max_page ) { - unsigned long *esp; SH_LOG("mark_dirty OOR! mfn=%x pfn=%lx max=%x (mm %p)", mfn, pfn, m->shadow_dirty_bitmap_size, m ); SH_LOG("dom=%p caf=%08x taf=%08x\n", frame_table[mfn].u.inuse.domain, frame_table[mfn].count_info, frame_table[mfn].u.inuse.type_info ); - __asm__ __volatile__ ("movl %%esp,%0" : "=r" (esp) : ); - show_trace(esp); } #endif -- 2.30.2